Moore’s Law might have been struggling recently but there’s no stopping universities churning out bigger and bigger chips
Researchers at Princeton University want to give a 32nm 25 core open source processor called “Piton” some serious bite and they have in mind a 200,000-core computer crammed with up to 8,000 64-bit Piton chips. But while it’s not expected to happen any time soon that’s one of the possible scenario for Piton, a chip which is designed to be flexible and quickly scalable, and that will have to ensure the giant collection of cores are in sync when processing applications in parallel.
The Princeton teams’ goal was to design a chip that could be used in large data centers to handle social networking requests, search and hyper scale cloud services because at the moment the response time for many of these applications are still tied to the horsepower of servers in data centers.
Piton is a rare breed of open-source processor based on the OpenSparc design, which is a modified version of Oracle’s OpenSparc T1 processor and the team are already busy at work designing a whole variety of new architectures. One of the more notable architectures under development is RISC-V, which is being used by SiFive to design a new processor but some open-source processor designs are designed for fun. For example, the Open Core Foundation is trying to provide an open-source design for the SH2 processor, which was in Sega’s 1994 Saturn gaming console.
Companies can take the open-source designs, tweak them, and fabricate chips in factories. Alternately, the chip can be simulated by putting the programmable logic on FPGAs (field-programmable gate arrays), which will then mimic the functionality of the multi-core CPU.
It’s interesting that the researchers chose SPARC as the architecture of choice for it’s design. SPARC is used by Oracle in its high-end servers designed for databases, but the popularity of the architecture is waning with Fujitsu recently stating that it was dropping SPARC in favour of ARM for servers, specifically for the Post-K supercomputer it will deploy in Japan in 2020.
One Piton chip has 25 cores broken up in five lines, a topology widely referred to as a mesh design. Each core operates at 1GHz. Multiple chips in an array can be daisy-chained system through a “bridge” that sits on top of the chip structure. The bridge also links the chip to DRAM and storage.
The mesh design isn’t a new idea as it has been used in chips from companies like Tilera, which is now a part of Mellanox. But what’s unique about Piton is the distributed cache and unidirectional links that would pull all cores together in a large server. The cores also share memory. Each core has 64KB of L2 cache, totalling 1.6MB for the chip and a mini-router in each core facilitates fast communication with each of the other cores. Each core also has a Floating Point Unit (FPU), mostly for large-scale parallel computing.
Across industry the core count in CPUs is climbing, especially in server and gaming chips, in order to provide more computing horsepower. AMD’s upcoming Zen based chips will have up to 32 cores, while Intel’s latest Xeon E7 server chips have up to 24 cores but the Princeton researchers claim Piton to be the largest chip in academia, with up to 460 million transistors – but notably not the largest number of cores in a chip which currently belongs to a 1,000 core chip called the KiloCore which was designed by researchers at the VLSI Computing Lab at University of California, Davis.